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NAND04GA3C2A NAND04GW3C2A
4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
Features
High density multi-level Cell (MLC) NAND Flash memories: - Up to 128 Mbit spare area - Cost effective solutions for mass storage applications NAND interface - x8 bus width - Multiplexed Address/ Data Supply voltages - VDD = 2.7 to 3.6V core supply voltage for Program, Erase and Read operations. - VDDQ = 1.7 to 1.95 or 2.7 to 3.6V for I/O buffers. Page size: (2048 + 64 spare) Bytes Block size: (256K + 8K spare) Bytes Page Read/Program - Random access: 60s (max) - Sequential access: 60ns(min) - Page Program Operation time: 800s (typ) Cache Read mode - Internal Cache Register to improve the read throughput Fast Block Erase - Block erase time: 1.5ms (typ) Status Register Electronic Signature Serial Number option Product List
Reference NAND04Gx3C2A NAND04GW3C2A Part Number NAND04GA3C2A 4 Gbits Density

TSOP48 12 x 20mm
Chip Enable `don't care' - for simple interface with microcontroller Data Protection - Hardware Program/Erase locked during power transitions Embedded Error Correction Code (ECC) - Internal ECC accelerator - Easy ECC Command Interface Data integrity - 10,000 Program/Erase cycles (with ECC) - 10 years Data Retention ECOPACK(R) package available Development tools - Bad Blocks Management and Wear Leveling algorithms - File System OS Native reference software - Hardware simulation models

Table 1.
November 2006
Rev 2
1/51
www.st.com 1
NAND04GA3C2A, NAND04GW3C2A
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSSQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 4.4 4.5 4.6 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 6
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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NAND04GA3C2A, NAND04GW3C2A
6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 25 P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SR4, SR3, SR2 and SR1 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . 25
6.11
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 8 9
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Embedded ECC accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 9.2 9.3 9.4 9.5 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5.1 9.5.2 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 11 12
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 33 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1 Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 46
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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NAND04GA3C2A, NAND04GW3C2A
14 15
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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NAND04GA3C2A, NAND04GW3C2A
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 33 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC Characteristics, VDDQ 3V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC Characteristics for Command, Address, Data Input, VDDQ 3V Devices . . . . . . . . . . . 37 AC Characteristics for Operations, VDDQ 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 48 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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NAND04GA3C2A, NAND04GW3C2A
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 Connections x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Program/Erase Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Program/Erase Disable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . . . 47 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 48
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NAND04GA3C2A, NAND04GW3C2A
1 Summary description
1
Summary description
The NAND04GA3C2A and NAND04GW3C2A are a Multi-level Cell(MLC) devices from the NAND Flash 2112 Byte Page family of non-volatile Flash memories. The devices are offered in 1.8V and 3V VDDQ I/O power supplies. The core voltage is 3V VDD. The size of a Page is 2112 Bytes (2048 + 64 spare). The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 10,000 cycles. The devices also have hardware security features; a Write Protect pin is available to give hardware protection against Program and Erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. Each device has a Cache Read feature which improves the read throughput for large files. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read. All devices have the Chip Enable Don't Care feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation There is the option of a Unique Identifier (serial number), which allows each device to be uniquely identified. It is subject to an NDA (Non Disclosure Agreement) and is therefore not described in the datasheet. For more details of this option contact your nearest ST Sales office. The NAND04GA3C2A and NAND04GW3C2A are available in a TSOP48 (12 x 20mm) package. In order to meet environmental requirements, ST offers the devices in ECOPACK(R) packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. For information on how to order these options refer to Table 22: Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to '1'. See Table 2: Product Description, for all the devices available in the family.
Table 2.
Product Description
Timings Bus Width Page Size Block Size Memory Array Operating Voltage VDD Operating Voltage VDDQ
Reference
Part Number
Density
Random Access (max)
Sequential Access (min)
Page Program (typ)
Block Erase (typ)
Package
NAND04GW3C2A NAND04Gx3C2A NAND04GA3C2A 4Gbits x8
2048+ 64 Bytes
256K+ 8K Bytes
128 Pages x 2048 Blocks
2.7 to 3.6V
2.7V to 3.6V 60s 60ns 800s 1.5ms TSOP48 1.7V to 1.95V
2.7 to 3.6V
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1 Summary description Figure 1. Logic Block Diagram
NAND04GA3C2A, NAND04GW3C2A
Address Register/Counter AL CL W E WP R X Decoder
Command Interface Logic
P/E/R Controller High Voltage Generator
NAND Flash Memory Array
Page Buffer Command Register Cache Register Y Decoder Data Register Buffers RB I/O
AI11009b
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NAND04GA3C2A, NAND04GW3C2A Figure 2. Logic diagram
1 Summary description
VDD
VDDQ
E I/O0 - I/O7 x8 R W AL CL WP NAND04GA3C2A NAND04GW3C2A
RB
VSS
VSSQ
AI12702b
Table 3.
I/O0 - I/O7 CL AL E R W WP RB VDD VDDQ VSS VSSQ NC DU
Signal Names
Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy (open drain output) Power supply I/O Power Ground I/O Ground No Connection Do Not Use
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1 Summary description Figure 3. TSOP48 Connections x8 devices
NAND04GA3C2A, NAND04GW3C2A
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
NAND04GA3C2A 12 NAND04GW3C2A 37 13 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDDQ VSSQ NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
24
25
AI12703b
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NAND04GA3C2A, NAND04GW3C2A
2 Memory array organization
2
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 128 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store software flags or Bad Block identification. The pages are split into a 2048 Byte main area and a spare area of 64 Bytes.Refer to Figure 4: Memory Array Organization.
2.1
Bad blocks
The NAND04GA3C2A and NAND04GW3C2A devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Section 9.1: Bad block management for more details). Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management and Block Replacement (refer to Section 9: Software algorithms).
Table 4.
Valid Blocks
Density of Device 4 Gbits Min 2008 Max 2048
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2 Memory array organization Figure 4. Memory Array Organization
NAND04GA3C2A, NAND04GW3C2A
Block = 128 Pages Page = 2112 Bytes (2,048 + 64)
a Sp
re
Are
a
Main Area Block Page
8 bits 2048 Bytes 64 Bytes
Page Buffer, 2112 Bytes 2,048 Bytes
64 Bytes
8 bits
AI12704
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NAND04GA3C2A, NAND04GW3C2A
3 Signal Descriptions
3
Signal Descriptions
See Figure 1: Logic Block Diagram, and Table 3: Signal Names, for a brief overview of the signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled.
3.2
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
3.3
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.4
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, vIH, while the device is busy, the device remains selected and does not go into standby mode.
3.5
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one.
3.6
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10s (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.
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3 Signal Descriptions
NAND04GA3C2A, NAND04GW3C2A
3.7
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.8
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Section 12.1: Ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor.
3.9
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for operations (read, program and erase).
3.10
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
3.11
VSSQ
VSSQ is the ground reference for the I/O power supply. It must be connected to the system ground.
3.12
VDDQ
VDDQ provides power to the I/O buffers.
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NAND04GA3C2A, NAND04GW3C2A
4 Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5: Bus Operations, for a summary. Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 13 and Table 19 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Five bus cycles are required to input the addresses (refer to Table 6: Address insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 14 and Table 19 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed. Data is only accepted when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 15 and Table 19 for details of the timing requirements.
4.4
Data Output
Data Output Bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signature and the Unique Identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 16 and Table 20 for details of the timings requirements.
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4 Bus operations
NAND04GA3C2A, NAND04GW3C2A
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
The memory enters Standby mode by driving Chip Enable, E, High. In standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
Table 5.
Bus Operations
E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(1) X VIH X VIL VIL/VDD I/O0 - I/O7 Command Address Data Input Data Output X X
Bus Operation Command Input Address Input Data Input Data Output Write Protect Standby
1. WP must be VIH when issuing a Program or Erase command.
Table 6.
Bus Cycle 1st 2nd 3rd 4th 5th
Address insertion(1)
I/O7 A7 VIL A19 A27 VIL I/O6 A6 VIL A18 A26 VIL I/O5 A5 VIL A17 A25 VIL I/O4 A4 VIL A16 A24 VIL I/O3 A3 A11 A15 A23 VIL I/O2 A2 A10 A14 A22 VIL I/O1 A1 A9 A13 A21 A29 I/O0 A0 A8 A12 A20 A28
1. Any additional address input cycles will be ignored.
Table 7.
Address Definitions
Address A0 - A11 A12 - A18 A19 - A29 Definition Column Address Page Address Block Address
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NAND04GA3C2A, NAND04GW3C2A
5 Command Set
5
Command Set
All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 8: Commands.
Table 8.
Commands
Bus Write Operations(1) Command 1st CYCLE 00h(2) 05h 00h 34h 80h 85h 60h FFh 90h 70h 2nd CYCLE 30h E0h 31h - 10h - D0h - - - 3rd CYCLE - - - - - - - - - - 4th CYCLE - - - - - - - - - - Yes Yes Yes(3) Commands accepted during busy
Read Random Data Output Cache Read Exit Cache Read Page Program (Sequential Input default) Random Data Input Block Erase Reset Read Electronic Signature Read Status Register
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. For consecutive read operations the 00h command does not need to be repeated. 3. Only when a Cache Read operation is ongoing.
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6 Device operations
NAND04GA3C2A, NAND04GW3C2A
6
Device operations
The following section gives the details of the device operations.
6.1
Read memory array
At Power-Up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see Table 8: Commands. Once a Read command is issued, subsequent consecutive Read commands only require the confirm command code (30h). Once a Read command is issued two types of operations are available: Random Read and Page Read.
6.2
Random Read
Each time the Read command is issued the first read is Random Read.
6.3
Page read
After the first Random Read access, the page data (2112 Bytes) is transferred to the Page Buffer in a time of tWHBH (refer to Table 20 for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during Cache Read operations.
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NAND04GA3C2A, NAND04GW3C2A Figure 5. Read Operations
6 Device operations
CL
E
W
AL
R tBLBH1 RB
I/O
00h
Command Code
Address Input
30h
Command Code
Data Output (sequentially)
Busy Ai11016
1. Highest address depends on device density.
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6 Device operations Figure 6. Random Data Output
NAND04GA3C2A, NAND04GW3C2A
tBLBH1
(Read Busy time)
RB Busy
R
I/O
000h Cmd Code
Address Inputs
30h Cmd Code
Data Output
05h Cmd Code
Address Inputs
E0h Cmd Code
Data Output
5 Add cycles Row Add 1,2,3 Col Add 1,2 Spare Area
2Add cycles Col Add 1,2 Spare Area
Main Area
Main Area
ai08658b
6.4
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page into the Cache Register. An Cache Read operation consists of three steps (see Table 8): 1. 2. 3. One bus cycle is required to setup the Cache Read command (the same as the standard Read command). Five bus cycles are then required to input the Start Address (refer to Table 6). One bus cycle is required to issue the Cache Read confirm command to start the P/E/R Controller.
The Start Address must be at the beginning of a page (Column Address = 000h, see Table 7.). This allows the data to be output uninterrupted after the latency time (tBLBH1), see Figure 7.
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6 Device operations
The Ready/Busy signal can be used to monitor the start of the operation. During the latency period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if the device is internally downloading page n+1. Once the Cache Read operation has started, the Status Register can be read using the Read Status Register command. During the operation, SR5 can be read, to find out whether the internal reading is ongoing (SR5 = `0'), or has completed (SR5 = `1'), while SR6 indicates whether the Cache Register is ready to download new data. To exit the Cache Read operation an Exit Cache Read command must be issued (see Table 8). Figure 7. Cache Read Operation
(Read Busy time)
tBLBH1
RB Busy I/O
00h
Address Inputs
31h
1st page
2nd page
3rd page
last page
34h
Read Setup Code
Cache Read Confirm Code
Block N Data Output
Exit Cache Read Code
ai08661
6.5
Page Program
The Page Program operation is the standard operation to program data to the memory array. Generally, data is programmed sequentially, however the device does support Random Input within a page. The memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 2112) can be programmed. Only one consecutive partial page program operations is allowed on the same page. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page.
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6 Device operations
NAND04GA3C2A, NAND04GW3C2A
6.6
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block. For Sequential Input each Page Program operation comprises five steps: 1. 2. 3. 4. 5. One bus cycle is required to setup the Page Program (Sequential Input) command (see Table 8). Five bus cycles are then required to input the program address (refer to Table 6). The data is then loaded into the Data Registers. One bus cycle is required to issue the Page Program confirm command to start the P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3. The P/E/R Controller then programs the data into the array.
6.7
Random Data input
During a Sequential Input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required to issue the command: 1. 2. One bus cycle is required to setup the Random Data Input command (see Table 8). Two bus cycles are then required to input the new column address (refer to Table 6).
Random Data Input can be repeated as often as required in any given page. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/E/R Controller bit SR6 is set to `1' and the Ready/Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface. Figure 8. Page Program Operation
(Program Busy time)
tBLBH2
RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0
Read Status Register
ai08659
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NAND04GA3C2A, NAND04GW3C2A Figure 9. Random Data Input During Sequential Data Input
6 Device operations
(Program Busy time)
tBLBH2
RB Busy I/O 80h Cmd Code Address Inputs Data Intput 85h Cmd Code Address Inputs 2 Add cycles Col Add 1,2 Data Input 10h Confirm Code 70h SR0
Read Status Register
5 Add cycles Row Add 1,2,3 Col Add 1,2
Main Area
Spare Area
Main Area
Spare Area
ai08664
6.8
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to `1'. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 10: 1. 2. 3. One bus cycle is required to setup the Block Erase command. Only addresses A19 to A30 are used, the other address inputs are ignored. Three bus cycles are then required to load the address of the block to be erased. Refer to Table 7 for the block addresses of each device. One bus cycle is required to issue the Block Erase confirm command to start the P/E/R Controller.
The operation is initiated on the rising edge of write Enable, W, after the confirm command is issued. The P/E/R Controller handles Block Erase and implements the verify process. During the Block Erase operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/E/R Controller bit SR6 is set to `1' and the Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit SR0 is `0', otherwise it is set to `1'.
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6 Device operations Figure 10. Block Erase Operation
NAND04GA3C2A, NAND04GW3C2A
tBLBH3
(Erase Busy time)
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0
Read Status Register
ai07593
6.9
Reset
The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tWHBH1 after the Reset command is issued. The value of tWHBH1 depends on the operation that the device was performing when the command was issued, refer to Table 20 for the values.
6.10
Read Status Register
The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new Read command must be issued to continue with a Page Read operation. Refer to Table 9 where Status Register bits are summarized. It should also be read in conjunction with the following text descriptions.
6.10.1
Write Protection Bit (SR7)
The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to `1' the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to `0' the device is protected and program or erase operations are not allowed.
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6 Device operations
6.10.2
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation. During Cache Read operations SR6 acts as a Cache Ready/Busy bit, which indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to accept new data. During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready).
6.10.3
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active; when the bit is set to `1', the P/E/R Controller is inactive.
6.10.4
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to `0' the operation has completed successfully.
6.10.5
SR4, SR3, SR2 and SR1 are Reserved
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6 Device operations Table 9.
Bit SR7
NAND04GA3C2A, NAND04GW3C2A
Status Register Bits
Name Write Protection '0' Program/ Erase/ Read Controller '1' '0' '1' Cache Ready/Busy '0' Cache Register busy (Cache Read only) P/E/R C inactive P/E/R C active Program/ Erase/ Read Controller(2) Reserved '1' '0' Don't Care `1' Generic Error `0' No Error - operation successful Error - operation failed Protected P/E/R C inactive, device ready P/E/R C active, device busy Cache Register ready (Cache Read only) Logic Level '1' Not Protected Definition
SR6(1)
SR5 SR4, SR3, SR2, SR1 SR0(1)
1. The SR6 bit and SR0 bit have a different meaning during Cache Read operations. 2. Only valid for Cache Read operations, for other operations it is same as SR6.
6.11
Read Electronic Signature
The device contains a Manufacturer Code and Device Code. To read these codes three steps are required: 1. 2. 3. One Bus Write cycle to issue the Read Electronic Signature command (90h) One Bus Write cycle to input the address (00h) Four Bus Read Cycles to sequentially output the data (as shown in Table 10: Electronic Signature). Electronic Signature
Byte/Word 1 Part Number Manufacturer Code 20h 20h Byte/Word 2 Byte 3 Device code DCh DCh (see Table 11) 84h 25h NAND04GW3C2A 84h Byte 4 (see Table 12)
Table 10.
NAND04GA3C2A
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NAND04GA3C2A, NAND04GW3C2A Table 11.
I/O
6 Device operations
Electronic Signature Byte 3
Definition Value 00 01 10 11 00 01 10 11 00 01 10 11 10 Description 1 2 4 8 2-level cell 4-level cell 8-level cell 16-level cell 1 2 4 8
I/O1-I/O0
Internal Chip number
I/O3-I/O2
Cell Type
I/O5-I/O4
Number of simultaneously programmed pages
I/O7-I/O6
Reserved
Table 12.
I/O
Electronic Signature Byte 4
Definition Value 00 01 10 11 0 1 00 10 01 11 00 01 10 11 0 1 Description 1 KBytes 2 KBytes Reserved Reserved 8 16 50ns 30ns Reserved Reserved 64 KBytes 128 KBytes 256 KBytes Reserved x8 x16
I/O1-I/O0
Page size (Without Spare Area) Spare area size (Byte / 512 Byte)
I/O2
I/O7, I/O3
Minimum sequential access time
I/O5-I/O4
Block size (without Spare Area)
I/O6
Organization
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7 Data Protection
NAND04GA3C2A, NAND04GW3C2A
7
Data Protection
The device has hardware features to protect against Program and Erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations. It is recommended to keep WP at VIL during power-up and powerdown.
8
Embedded ECC accelerator
The NAND04GA3C2A and NAND04GW3C2A devices include a powerful embedded Error Correction Code (ECC) accelerator. This feature ensures high memory reliability and fast data throughput while simplifying the design of the memory application. If the embedded ECC accelerator cannot be used, it is strongly recommended to use an external hardware accelerator to maintain the same data throughput. If this proves to be impossible, a software ECC can be implemented. However, this solution will result in lower performance compared to the hardware ECC solution. The ECC operation and command set are described in a dedicated application note. Please contact the nearest STMicroelectronics sales office for further details.
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9 Software algorithms
9
Software algorithms
This section gives information on the software algorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 14 for value) and it is recommended to implement Garbage Collection, Wear-Leveling and Error Correction Code algorithms to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application ST Microelectronics can provide a File System OS Native reference software, which supports the basic commands of file management. Contact the nearest ST Microelectronics sales office for more details.
9.1
Bad block management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block, where the 1st Byte in the spare area of the last page, does not contain FFh, is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 11.
9.2
Block replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 13 for the recommended procedure to follow if an error occurs during an operation.
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9 Software algorithms Table 13. Block Failure
Operation Erase Program Read
1. Example: 4 bit correction per 528 Bytes.
NAND04GA3C2A, NAND04GW3C2A
Recommended Procedure Block Replacement Block Replacement or ECC(1) ECC(1)
Figure 11. Bad Block Management Flowchart
START
Block Address = Block 0
Increment Block Address Update Bad Block table
Data = FFh? YES
NO
Last block? YES
NO
END
AI07588C
Figure 12. Garbage Collection
Old Area New Area (After GC)
Valid Page Invalid Page Free Page (Erased)
AI07599B
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9 Software algorithms
9.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm. In a Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 12).
9.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm to monitor and spread the number of write cycles per block. In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: 1. 2. First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data.
The Second Level Wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
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9 Software algorithms
NAND04GA3C2A, NAND04GW3C2A
9.5
9.5.1
Hardware simulation models
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware.
9.5.2
IBIS simulations models
IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS.
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NAND04GA3C2A, NAND04GW3C2A
10 Program and erase times and endurance cycles
10
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 14
Table 14.
Program, Erase Times and Program Erase Endurance Cycles
NAND04GA3C2A, NAND04GW3C2A Parameters Min Typ 800 1.5 10,000 10 Max 2000 3 s ms cycles years Unit
Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention
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11 Maximum rating
NAND04GA3C2A, NAND04GW3C2A
11
Maximum rating
Stressing the device above the ratings listed in Table 15: Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 15.
Absolute Maximum Ratings
Value Parameter Min Max 125 150 2.7 4.6 4.6 C C V V V Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage 1.8V, VDDQ devices 3 V, VDDQ devices - 50 - 65 - 0.6 - 0.6 - 0.6 Unit
Symbol TBIAS TSTG VIO(1) VDD
1. Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.
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12 DC and AC parameters
12
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 16: Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The DC and AC characteristics for VDDQ 1.8V devices are not yet available.
Table 16.
Operating and AC Measurement Conditions
Parameter NAND04GA3C2A, NAND04GW3C2A Min 1.8V, VDDQ devices 1.7 2.7 0 -40 30 50 0 0.4 0.9 1.5 8.35 5 VDD 2.4 Max 1.95 3.6 70 85 V V C C pF pF V V V V k ns Units
Supply Voltage (VDD) 3V, VDDQ devices Grade 1 Ambient Temperature (TA) Grade 6 1.8V VDDQ devices Load Capacitance (CL) (1 TTL GATE and CL) 3V, VDDQ devices (2.7 - 3.6V) 1.8V, VDDQ devices Input Pulses Voltages 3V, VDDQ devices 1.8V, VDDQ devices Input and Output Timing Ref. Voltages 3V, VDDQ devices Output Circuit Resistor Rref Input Rise and Fall Times
Table 17.
Symbol CIN CI/O
Capacitance(1)
Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VIL = 0V Typ Max 10 10 Unit pF pF
1. TA = 25C, f = 1 MHz. CIN and CI/O are not 100% tested.
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12 DC and AC parameters Table 18.
Symbol IDD1 IDD2 IDD3
IDD4
NAND04GA3C2A, NAND04GW3C2A
DC Characteristics, VDDQ 3V Devices(1)
Parameter Sequential Read Program Erase Standby current (TTL) Standby Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VIH, WP=0/VDD E=VDD-0.2, WP=0/VDD VIN= 0 to 3.6V VOUT= 0 to 3.6V IOH = -400A IOL = 2.1mA VOL = 0.4V 2.0 -0.3 2.4 8 10 10 Min Typ 10 20 15 Max 20 30 20 1 50 10 10 VDD+0.3 0.8 0.4 Unit mA mA mA mA A A A V V V V mA
Operating Current
IDD5 ILI ILO VIH VIL VOH VOL IOL (RB)
1. DC Characteristics for VDDQ 1.8V devices are still to be determined.
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NAND04GA3C2A, NAND04GW3C2A Table 19.
Symbol tALLWH tALHWH tCLHWH tCLLWH tDVWH tELWH tWHALH tWHALL tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL
12 DC and AC parameters
AC Characteristics for Command, Address, Data Input, VDDQ 3V Devices(1)
Alt. Symbol tALS Parameter Address Latch Low to Write Enable High AL Setup time Address Latch High to Write Enable High Command Latch High to Write Enable High tCLS tDS tCS tALH CL Setup time Command Latch Low to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable High Write Enable High to Address Latch High AL Hold time Write Enable High to Address Latch Low Write Enable High to Command Latch High tCLH tDH tCH tWH tWP tWC CL hold time Write Enable High to Command Latch Low Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data Hold time E Hold time W High Hold time W Pulse Width Write Cycle time Min Min Min Min Min 15 10 20 40 60 ns ns ns ns ns Min 10 ns Min 15 ns Data Setup time E Setup time Min Min 20 30 ns ns Min 20 ns Min 40 ns 3V I/O Unit
1. AC Characteristics for VDDQ 1.8V devices are still to be determined.
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12 DC and AC parameters Table 20.
Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 tBLBH4 Write Enable High to Ready/Busy High tPROG tBERS Ready/Busy Low to Ready/Busy High
NAND04GA3C2A, NAND04GW3C2A
AC Characteristics for Operations, VDDQ 3V Devices(1)
Alt. Symbol tAR tRR Address Latch Low to Read Enable Low Parameter Read Electronic Signature Read cycle Min Min Min Max Max Max Max Max Max Max Min Min Max Max Min Max Min Min 3V I/O 20 20 20 60 2000 3 5 20 40 200 15 0 30 50 20 30 40 60 Unit ns ns ns s s ms s s s s ns ns ns ns ns ns ns ns
Ready/Busy High to Read Enable Low Read Busy time Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read
tWHBH1
tRST
Reset Busy time, during program Reset Busy time, during erase
tCLLRL tDZRL tEHQZ tELQV tRHRL tRHQZ tRLRH tRLRL tRLQV tWHBH tWHBL tWHRL tVHWH
(3)
tCLR tIR tCHZ tCEA tREH tRHZ tRP tRC tREA tR tWB tWHR tWW
Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Read Enable High to Read Enable Low Read Enable High Hold time
Read Enable High to Output Hi-Z Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time(2) Read Busy time
Max
45
ns
Max Max Min Min
60 100 80 100 100
s ns ns ns ns
Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Write Protection time
tVLWH(3)
Min
1. AC Characteristics for VDDQ 1.8V devices are still to be determined. 2. ES = Electronic Signature. 3. WP High to W High during Program/Erase Enable operations.
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NAND04GA3C2A, NAND04GW3C2A Figure 13. Command Latch AC Waveforms
12 DC and AC parameters
CL tCLHWH
(CL Setup time)
tWHCLL
(CL Hold time)
tELWH
H(E Setup time)
tWHEH
(E Hold time)
E tWLWH W tALLWH
(ALSetup time)
tWHALH
(AL Hold time)
AL tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai12705
Figure 14. Address Latch AC Waveforms
(CL Setup time)
tCLLWH
CL tELWH
(E Setup time)
tWLWL
tWLWL
tWLWL
tWLWL
E tWLWH W tWHWL tALHWH
(AL Setup time)
tWLWH
tWLWH
tWLWH
tWLWH
tWHWL
tWHWL
tWHWL
tWHALL
(AL Hold time)
tWHALL
tWHALL
tWHALL
AL tDVWH tDVWH tWHDX
(Data Hold time)
(Data Setup time)
tDVWH tWHDX Adrress cycle 2 Adrress cycle 3
tDVWH tWHDX Adrress cycle 4
tDVWH tWHDX Adrress cycle 5
ai12706
tWHDX
I/O
Adrress cycle 1
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12 DC and AC parameters Figure 15. Data Input Latch AC Waveforms
NAND04GA3C2A, NAND04GW3C2A
tWHCLH
(CL Hold time)
CL tWHEH
(E Hold time)
E
(ALSetup time)
tALLWH
tWLWL AL tWLWH W tDVWH
(Data Setup time)
tWLWH
tWLWH
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX tWHDX
I/O
Data In 0
Data In 1
Data In Last
ai12707
1. Last Data In is 2111b.
Figure 16. Sequential Data Output after Read AC Waveforms
tRLRL
(Read Cycle time)
E tRHRL
(R High Holdtime)
tEHQZ
R tRHQZ tRLQV
(R Accesstime)
tRHQZ tRLQV
tRLQV
I/O tBHRL RB
Data Out
Data Out
Data Out
ai08031
1. CL = Low, AL = Low, W = High.
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NAND04GA3C2A, NAND04GW3C2A Figure 17. Read Status Register AC Waveform
tCLLRL CL tWHCLL tCLHWH E tELWH tWLWH W tWHRL R tDZRL tDVWH
(Data Setup time)
12 DC and AC parameters
tWHEH
tELQV tEHQZ
tWHDX
(Data Hold time)
tRLQV
tRHQZ
I/O
70h
Status Register Output
ai12708
Figure 18. Read Electronic Signature AC Waveform
CL
E
W
AL tALLRL1
R
(Read ES Access time)
tRLQV
I/O
90h Read Electronic Signature Command
00h 1st Cycle Address
Byte1 Man. code
Byte2 Device code
Byte3
Byte4
see Note.1
ai08667b
1. Refer to Table 10 for the values of the Manufacturer and Device Codes, and to Table 11 and Table 12 for the information contained in Byte3 and Byte 4.
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12 DC and AC parameters Figure 19. Page Read Operation AC Waveform
NAND04GA3C2A, NAND04GW3C2A
CL
E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL
(Read Cycle time)
tEHQZ
tRHQZ
R tRLRH tBLBH1 RB
I/O
00h
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N Add.N cycle 4 cycle 5
30h
Data N
Data N+1
Data N+2
Data Last
Command Code
Address N Input
Busy
Data Output from Address N to Last Byte or Word in Page
Ai11018b
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NAND04GA3C2A, NAND04GW3C2A Figure 20. Page Program AC Waveform
12 DC and AC parameters
CL
E tWLWL
(Write Cycle time)
tWLWL
tWLWL
W tWHBL tBLBH2
(Program Busy time)
AL
R
I/O
80h
Add.N Add.N Add.N Add.N Add.N cycle1 cycle 2 cycle 3 cycle 4 cycle 5
N
Last
10h
70h
SR0
RB Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program Read Status Register
Ai11019
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12 DC and AC parameters Figure 21. Block Erase AC Waveform
NAND04GA3C2A, NAND04GW3C2A
CL
E tWLWL
(Write Cycle time)
W tWHBL AL
(Erase Busy time)
tBLBH3
R
I/O
60h
Add. Add. Add. cycle 1 cycle 2 cycle 3
D0h
70h
SR0
RB Block Erase Setup Command Confirm Code Block Erase Read Status Register
ai08038c
Block Address Input
Figure 22. Reset AC Waveform
W
AL CL
R I/O FFh tWHBH1
(Reset Busy time)
RB
ai08043b
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NAND04GA3C2A, NAND04GW3C2A Figure 23. Program/Erase Enable Waveform
12 DC and AC parameters
W tVHWH WP
RB
I/O
80h
10h
ai12709
Figure 24. Program/Erase Disable Waveform
W tVLWH WP High RB
I/O
80h
10h
ai12710
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12 DC and AC parameters
NAND04GA3C2A, NAND04GW3C2A
12.1
Ready/busy signal electrical characteristics
Figure 25, Figure 26 and Figure 27 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation:
(V - ) DDmax V OLmax R P min = ------------------------------------------------------------+ IL I OL
So,
1.85V R P min ( 1.8V ) = -------------------------3mA + I L 3.2V R P min ( 3V ) = -------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 25. Ready/Busy AC Waveform
ready VDD VOH VOL busy tf tr
AI07564B
Figure 26. Ready/Busy Load Circuit
VDD
RP
ibusy
DEVICE RB Open Drain Output
VSS
AI07563B
46/51
NAND04GA3C2A, NAND04GW3C2A
12 DC and AC parameters
Figure 27. Resistor Value Versus Waveform Timings For Ready/Busy Signal
VDDQ = 1.8V, CL = 30pF 400 4 400
VDDQ = 3.3V, CL = 100pF 4
400
300 tr, tf (ns)
3 ibusy (mA) tr, tf (ns)
300
2.4
300
3 ibusy (mA)
ai11014
200
1.7
2
200
200
2
120
1.2
100
30 1.7
0.85 60 1.7
90 0.57 1.7
1
0.43 1.7
100
100 3.6 3.6
0.8
1
0.6
0
0
3.6
3.6
1
2 RP (K)
3
4
1
2 RP (K)
3
4
tf
tr
ibusy
1. T = 25C.
47/51
13 Package mechanical
NAND04GA3C2A, NAND04GW3C2A
13
Package mechanical
Figure 28. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
1 48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
1. Drawing is not to scale.
Table 21.
Symbol
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
millimeters Typ Min Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.080 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0276 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283
A A1 A2 B C CP D1 E E1 e L L1 a
48/51
NAND04GA3C2A, NAND04GW3C2A
14 Part numbering
14
Table 22.
Example: Device Type
Part numbering
Ordering Information Scheme
NAND04GW3C2A N 1 E
NAND Flash Memory Density 04G = 4Gb Operating Voltage W = VDDQ = 2.7 to 3.6V A = VDDQ = 1.7V to 1.95V Bus Width 3 = x8 Family Identifier C = 2112 Bytes Page MLC Device Options 2 = Chip Enable Don't Care Enabled Product Version A = First Version Package N = TSOP48 12 x 20mm (all devices) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest ST Sales Office.
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15 Revision history
NAND04GA3C2A, NAND04GW3C2A
15
Revision history
Table 23.
Date 16-Mar-2006 09-Nov-2006
Document revision history
Revision 1 2 Initial release. NAND08GA2C2A and NAND08GW2C2A root part numbers removed. Changes
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NAND04GA3C2A, NAND04GW3C2A
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